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74VCX16838 Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
July 1997 Revised June 2005
74VCX16838 Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16838 contains sixteen non-inverting selectable buffered or registered paths. The device can be configured to operate in a registered, or flow through buffer mode by utilizing the register enable (REGE) and Clock (CLK) signals. The device operates in a 16-bit word wide mode. All outputs can be placed into 3-State through use of the OE Pin. These devices are ideally suited for buffered or registered 168 pin and 200 pin SDRAM DIMM memory modules. The 74VCX16838 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74VCX16838 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s Compatible with PC100 and PC133 DIMM module specifications s 1.65V-3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD (CLK to O n)
3.0 ns max for 3.0V to 3.6V VCC 4.0 ns max for 2.3V to 2.7V VCC 8.0 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal (Note 1) s Static Drive (IOH/IOL)
r24 mA @ 3.0V VCC r18 mA @ 2.3V VCC r6 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry s Ideal for SDRAM DIMM modules s Latch-up performance exceeds 300 mA s ESD performance:
Human body model ! 2000V Machine model ! 200V
Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74VCX16838MTD Package Number MTD48 Package Description 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names OE I0-I15 O0-O15 CLK REGE Description Output Enable Input (Active LOW) Inputs Outputs Clock Input Register Enable Input
(c) 2005 Fairchild Semiconductor Corporation
DS500034
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74VCX16838
Connection Diagram
Truth Table
Inputs CLK REGE H H L L X In H L H L X OE L L L L H Outputs On H L H L Z
n n
X X X
H Logic HIGH L Logic LOW X Don't Care, but not floating Z High Impedance n LOW-to-HIGH Clock Transition
Functional Description
The 74VCX16838 consists of sixteen selectable non-inverting buffers or registers with word wide modes. Mode functionality is selected through operation of the CLK and REGE pin as shown by the truth table. When REGE is held at a logic HIGH the device operates as a 16-bit register. Data is transferred from In to On on the rising edge of the CLK input. When the REGE pin is held at a logic LOW the device operates in a flow through mode and data propagates directly from the I to the O outputs. All outputs can be 3-STATE by holding the OE pin at a logic HIGH.
Logic Diagram
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74VCX16838
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 3) DC Input Diode Current (IIK) VI 0V DC Output Diode Current (IOK) VO 0V VO ! VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
0.5V to 4.6V 0.5V to 4.6V 0.5V to 4.6V 0.5V to VCC 0.5V 50 mA 50 mA 50 mA r50 mA r100 mA 65qC to 150qC
Recommended Operating Conditions (Note 4)
Power Supply Operating Data Retention Only Input Voltage Output Voltage (VO) Output in Active States Output in "OFF" State Output Current in IOH/IOL VCC VCC VCC 3.0V to 3.6V 2.3V to 2.7V 1.65V to 2.3V 0V to VCC 0V to 3.6V 1.65V to 3.6V 1.2V to 3.6V
0.3V to 3.6V
Free Air Operating Temperature (TA) Minimum Input Edge Rate ('t/'V) VIN 0.8V to 2.0V, VCC 3.0V
r24 mA r18 mA r6 mA 40qC to 85qC
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics (2.7V VCC d 3.6V)
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH IOH IOH IOH VOL LOW Level Output Voltage IOL IOL IOL IOL II IOZ IOFF ICC Input Leakage Current 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current Increase in ICC per Input Conditions VCC (V) 2.7-3.6 2.7-3.6 Min 2.0 0.8 VCC 0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 V V Max Units V V
100 PA 12 mA 18 mA 24 mA
100 PA 12 mA 18 mA 24 mA
2.7-3.6 2.7 3.0 3.0 2.7-3.6 2.7 3.0 3.0 2.7-3.6 2.7-3.6 0 2.7-3.6 2.7-3.6
0V d VI d 3.6V 0V d VO d 3.6V VI VI VIH VIH or VIL VCC or GND VCC 0.6V 0V d (VI, VO) d 3.6V VCC d (VI, VO) d 3.6V (Note 5)
r5.0 r10
10 20
PA PA PA PA PA
r20
750
'ICC
Note 5: Outputs disabled or 3-STATE only.
3
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74VCX16838
DC Electrical Characteristics (2.3V d VCC d 2.7V)
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH IOH IOH IOH VOL LOW Level Output Voltage IOL IOL IOL II IOZ IOFF ICC Input Leakage Current 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current Conditions VCC (V) 2.3-2.7 2.3-2.7 Min 1.6 0.7 VCC 0.2 2.0 1.8 1.7 0.2 0.4 0.6 V V Max Units V V
100 PA 6 mA 12 mA 18 mA
100 PA 12 mA 18 mA
2.3-2.7 2.3 2.3 2.3 2.3-2.7 2.3 2.3 2.3-2.7 2.3-2.7 0 2.3-2.7
V0 d VI d 3.6V 0V d VO d 3.6V VI VI VIH or VIL VCC or GND 0V d (VI, VO) d 3.6V VCC d (VI, VO) d 3.6V (Note 6)
r5.0 r10
10 20
PA PA PA PA
r20
Note 6: Outputs disabled or 3-STATE only.
DC Electrical Characteristics (1.65V d VCC 2.3V)
Symbol VIH VIL VOH VOL II IOZ IOFF ICC Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current IOH IOH IOL IOL Conditions VCC (V) 1.65 - 2.3 1.65 - 2.3 Min 0.65 u VCC 0.35 u V CC VCC 0.2 1.25 0.2 0.3 Max Units V V V V
100 PA 6 mA
100 PA 6 mA
1.65 - 2.3 1.65 1.65 - 2.3 1.65 1.65 - 2.3 1.65 - 2.3 0 1.65 - 2.3
0V d VI d 3.6V 0V d VO d 3.6V VI VI V IH or VIL V CC or GND 0V d (VI, VO) d 3.6V VCC d (VI, VO) d 3.6V (Note 7)
r5.0 r10
10 20
PA PA PA PA
r20
Note 7: Outputs disabled or 3-STATE only.
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74VCX16838
AC Electrical Characteristics (Note 8)
TA Symbol Parameter VCC Min fMAX tPHL, tPLH tPHL, tPLH tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tS tH tW tOSHL tOSLH Maximum Clock Frequency Propagation Delay In to On (REGE 0) Propagation Delay CLK to On (REGE 1) Propagation Delay REGE to On Output Enable Time Output Disable Time Setup Time Hold Time Pulse Width Output to Output Skew (Note 9) 250 0.8 0.8 0.8 0.8 0.8 1.0 0.7 1.5 0.5 2.5 3.0 3.0 3.5 3.5
40qC to 85qC, CL
VCC Min 200 1.0 1.0 1.0 1.0 1.0 1.0 0.7 1.5
30 pF, RL
500: VCC Min 100 1.8V r 0.15V Max MHz 7.0 8.0 8.0 9.4 7.0 ns ns ns ns ns ns ns ns 0.75 ns Units
3.3V r 0.3V Max
2.5V r 0.2V Max
3.5 4.0 4.0 4.7 3.9
1.5 1.5 1.5 1.5 1.5 2.5 1.0 4.0
0.5
Note 8: For CL
50PF, add approximately 300 ps to the AC maximum specification.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Extended AC Electrical Characteristics (Note 10)
TA Symbol Parameter Min tPHL, tPLH tPHL, tPLH tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tS tH Propagation Delay In to On (REGE Propagation Delay REGE to On Output Enable Time Output Disable Time Setup Time Hold Time 0) 1) 1.0 1.4 1.0 1.0 1.0 1.0 0.7 Propagation Delay CLK to On (REGE
0qC to 85qC, RL
CL
500: VCC 50 pF
3.3V r 0.3V Units Max 2.8 3.3 3.3 3.8 3.8 ns ns ns ns ns ns ns
Note 10: This parameter is guaranteed by characterization but not tested.
Dynamic Switching Characteristics
Symbol VOLP Parameter Quiet Output Dynamic Peak VOL CL 30 pF, VIH Conditions VCC, VIL 0V VCC (V) 1.8 2.5 3.3 VOLV Quiet Output Dynamic Valley VOL CL 30 pF, VIH VCC, VIL 0V 1.8 2.5 3.3 VOHV Quiet Output Dynamic Valley VOH CL 30 pF, VIH VCC, VIL 0V 1.8 2.5 3.3 TA
25qC
0.25 0.6 0.8
Typical
Units
V
0.25 0.6 0.8
1.5 1.9 2.2 V V
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VCC VI VI VCC Conditions 1.8V, 2.5V or 3.3V, VI 0V or VCC, VCC 0V or VCC, f 10 MHz, 0V or VCC TA
25qC
6 7 20
Typical
Units pF pF pF
1.8V, 2.5V or 3.3V
1.8V, 2.5V or 3.3V
5
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74VCX16838
AC Loading and Waveforms
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open 6V at VCC 3.3 r 0.3V; VCC x 2 at VCC 2.5 r 0.2V; 1.8V r 0.15V GND FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. Propagation Delay, Pulse Width and trec Waveforms
FIGURE 5. Setup Time, Hold Time and Recovery Time for Low Voltage Logic Symbol Vmi Vmo VX VY VCC 3.3V r 0.3V 1.5V 1.5V VOL 0.3V VOH 0.3V 2.5V r 0.2V VCC/2 VCC/2 VOL 0.15V VOH 0.15V 1.8V r 0.15V VCC/2 VCC/2 VOL 0.15V VOH 0.15V
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74VCX16838 Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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